Search found 436 matches
- Tue Dec 29, 2020 11:48 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Digilent Nexys A7-100T
- Replies: 0
- Views: 32046
Project Oberon Workstation on Digilent Nexys A7-100T
To help new users get started we have now made available, free of charge, a disk image, Verilog sources and a bitstream file specifically to run the Project Oberon Workstation on the Digilent Nexys A7-100T FPGA trainer board 'out-of-the-box'. This release is based on the Oberon sources (as at March ...
- Fri Dec 18, 2020 10:21 pm
- Forum: Astrobe for FPGA RISC5
- Topic: RISC5 Oberon now on the Artix 7-100T
- Replies: 0
- Views: 26447
RISC5 Oberon now on the Artix 7-100T
We have successfully implemented Astrobe Embedded Project Oberon on the XC7A100T FPGA device of the Xilinx Artix 7 family. This means that Astrobe can have 480 KBytes of RAM available to it. This is 2-3 times more than our other supported implementations, allowing for more / larger applications to b...
- Fri Dec 18, 2020 7:24 am
- Forum: Getting Started
- Topic: Very impressed with free (!!!) Astrobe for RISC5 FPGA
- Replies: 3
- Views: 17382
Re: Very impressed with free (!!!) Astrobe for RISC5 FPGA
There's also some useful information in Chapter 14 Building and maintenance tools of the Project Oberon book which is accessible from Astrobe for RISC5 > Help > Project Oberon. Note that you only need to rebuild the disk image if you modify and relink the inner core of the Project Oberon OS, which c...
- Tue Dec 15, 2020 8:59 am
- Forum: Getting Started
- Topic: Very impressed with free (!!!) Astrobe for RISC5 FPGA
- Replies: 3
- Views: 17382
Re: Very impressed with free (!!!) Astrobe for RISC5 FPGA
Thank you for your positive feedback. It is very much appreciated.
We haven't released the tools that we use to create the disk image but Andreas Pirklbauer, one of the other guys who has modified the OS has. You can find them at:
https://github.com/andreaspirklbauer/Ob ... ding-tools
We haven't released the tools that we use to create the disk image but Andreas Pirklbauer, one of the other guys who has modified the OS has. You can find them at:
https://github.com/andreaspirklbauer/Ob ... ding-tools
- Fri Sep 11, 2020 4:06 am
- Forum: Oberon Language
- Topic: Type compatibility rules summary.
- Replies: 2
- Views: 16987
Type compatibility rules summary.
An interesting question about the type compatibility rules was recently posted here but was deleted by the user. As it happened it actually highlighted a problem which was subsequently fixed in v7.2 of Astrobe. A good summary of Oberon's type compatibility rules which helps to answer these sorts of ...
- Fri Sep 04, 2020 6:15 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Can the limit on the number of record extension levels be increased?
- Replies: 1
- Views: 17885
Re: Can the limit on the number of record extension levels be increased?
There is now a compiler option 'Extension levels' on the Tools > Preference > Compiler tab page. This allows you to change the limit of the number of record extension levels from as little as zero to as many as 8. Be aware that it is a system-wide option. Each additional level incurs an overhead of ...
- Wed Mar 11, 2020 3:47 am
- Forum: Getting Started
- Topic: Timers Microseconds
- Replies: 3
- Views: 22403
Re: Timers Microseconds
That error message indicates that microsecond timing is not supported on TIM3 on your target microcontroller. Which microcontroller are you targeting?
- Sun Jan 19, 2020 11:50 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Configuring Buffer Sizes
- Replies: 2
- Views: 24103
Re: Configuring Buffer Sizes
You may well 'like' to have different buffer sizes and in theory it may be 'correct' but is it really worth all this effort? How many different buffers are you expecting? What are the minimum and maximum sizes? How many instances of the serial channels would there be? For your example I would simpli...
- Sat Dec 28, 2019 4:11 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: push {}
- Replies: 20
- Views: 92546
Re: push {}
Here's an example of how to test the trapping of UsageFault errors:
Code: Select all
MODULE TestTraps4;
IMPORT Main, Out, SYSTEM;
VAR
p: PROCEDURE;
x: INTEGER;
PROCEDURE P1();
BEGIN
Out.String("ok"); Out.Ln()
END P1;
BEGIN
P1();
SYSTEM.PUT(SYSTEM.ADR(p), SYSTEM.ADR(P1) + 1);
p()
END TestTraps4.
- Sat Dec 28, 2019 3:57 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: push {}
- Replies: 20
- Views: 92546
Re: push {}
Not by design and you didn't miss anything either. I wasn't aware of this - do you know of any reason why they are disabled by default? The following example code shows one way they could be enabled: CONST NVIC_SHCSR = MCU.NVICBase + 0D24H; VAR x: INTEGER; SYSTEM.GET(NVIC_SHCSR, x); BFI(x, 18, 16, 0...