Search found 444 matches
- Tue Oct 19, 2021 3:42 am
- Forum: Astrobe for FPGA RISC5
- Topic: v8.0 Astrobe for RISC5 has now been released
- Replies: 0
- Views: 76071
v8.0 Astrobe for RISC5 has now been released
v8.0 Astrobe for RISC5 has now been released. Developers can use Astrobe on Windows to edit and compile real-time Oberon applications. These can then be uploaded and executed on a minimal embedded version of the Project Oberon OS running on an FPGA board. A summary of the new features included in th...
- Fri Jul 30, 2021 4:30 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Programming STM32 through SWD
- Replies: 2
- Views: 19079
Re: Programming STM32 through SWD
Yes - you can program the STM32F746 through the SWD interface directly from the Astrobe IDE using the ST-LINK CLI. This was the sort of capability that we had in mind when we designed the user-configurable Tools menu. Edit your AstrobeM3-v7.2\Configs\Tools.ini file and add the following lines or som...
- Wed Jun 02, 2021 1:45 am
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Digilent Nexys 4 Rev B
- Replies: 6
- Views: 18248
Re: Project Oberon Workstation on Digilent Nexys 4 Rev B
This story has a happy ending as reported by Pablo on the ETH Oberon mailing list
http://lists.inf.ethz.ch/pipermail/oberon/2021/015888.html
http://lists.inf.ethz.ch/pipermail/oberon/2021/015888.html
- Tue Jun 01, 2021 9:59 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Self-unloading With Modules.Free?
- Replies: 2
- Views: 14278
Re: Self-unloading With Modules.Free?
Free should be used with great care and only when necessary. A situation where it is necessary and generally OK is when you are in the process of developing a new module and want to test it after making changes and recompiling. In that case you should have a good understanding of how the module work...
- Sun May 30, 2021 11:43 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Digilent Nexys 4 Rev B
- Replies: 6
- Views: 18248
Re: Project Oberon Workstation on Digilent Nexys 4 Rev B
Great! I'm pleased to hear that you have got it working. I'll add a note to the installation instructions to point out that the folder structure should be maintained when unzipping the Verilog files. We deliberately use the same folder structure as the official Project Oberon release. Is that why yo...
- Fri May 28, 2021 11:26 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Mapping to Nexys4 Cell RAM board
- Replies: 3
- Views: 14797
Re: Mapping to Nexys4 Cell RAM board
Thank you for the additional information. We used to supply the MCS files with the bitstream file but discovered that not only are these different for different boards, but also between different revisions of the same board :( Anbody else reading this should note the following: You need to refer to ...
- Fri May 28, 2021 11:07 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Digilent Nexys 4 Rev B
- Replies: 6
- Views: 18248
Re: Project Oberon Workstation on Digilent Nexys 4 Rev B
(To minimise any confusion I've created this new topic and moved the original message from the Arty A7-100 topic.) We do not have the older Nexys 4 Rev B board so we are unable to test Project Oberon Workstation on it. However, it appears to similar enough to the Nexys A7-100T (which we are able to ...
- Thu May 27, 2021 10:06 am
- Forum: Astrobe for FPGA RISC5
- Topic: Mapping to Nexys4 Cell RAM board
- Replies: 3
- Views: 14797
Re: Mapping to Nexys4 Cell RAM board
Make sure that you are only using the files supplied for Embedded Project Oberon if you are using the constraints file you attached here. These files must not be mixed with the files supplied for Project Oberon Workstation. The Embedded Project Oberon BootLoader ROM file is called prom.mem. You shou...
- Sat May 22, 2021 10:24 am
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Digilent Arty A7-100T
- Replies: 0
- Views: 32510
Project Oberon Workstation on Digilent Arty A7-100T
To help new users get started we have now made available, free of charge, a disk image, Verilog sources and bitstream file specifically to run the Project Oberon Workstation on the Digilent Arty A7-100T FPGA development board and associated Pmod modules 'out-of-the-box'. This release is based on the...
- Fri May 14, 2021 2:12 am
- Forum: RISC5
- Topic: Stimulus driven interrupts?
- Replies: 2
- Views: 100963
Re: Stimulus driven interrupts?
For anybody who is interested this discussion was continued on the ETH Oberon Mailing list:
http://lists.inf.ethz.ch/pipermail/oberon/2021/015803.html
http://lists.inf.ethz.ch/pipermail/oberon/2021/015803.html