Search found 103 matches

by gray
Tue Nov 21, 2023 11:18 am
Forum: Bug Reports
Topic: Stack Trace Considerations (M0)
Replies: 2
Views: 2406

Stack Trace Considerations (M0)

With Astrobe version 9.0, the useful stack trace functionality of can show false positives, ie. list procedure calls that don't belong in the call chain leading up to the run-time error. Consider this test code: MODULE TestError1; IMPORT Main; VAR x, y: INTEGER; PROCEDURE p1; VAR z: INTEGER; BEGIN y...
by gray
Fri Nov 17, 2023 9:54 am
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: Interrupt Handlers
Replies: 2
Views: 5625

Re: Interrupt Handlers

Wow. Smart. I am impressed. Thanks for that.
by gray
Thu Nov 16, 2023 12:26 pm
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: Interrupt Handlers
Replies: 2
Views: 5625

Interrupt Handlers

For the Cortex-M0, the prologue and epilogue generated for interrupt handlers is the same as for normal parameterless procedures. That is, they are the same for PROCEDURE p0; END p0; 0B500H push { lr } 046C0H nop 0BD00H pop { pc } 046C0H nop and PROCEDURE p1[0]; END p1; 0B500H push { lr } 046C0H nop...
by gray
Sat Jun 17, 2023 4:41 am
Forum: Astrobe for FPGA RISC5
Topic: SYSTEM.LDREG
Replies: 4
Views: 84635

Re: SYSTEM.LDREG

SYSTEM.LDREG is also used in Oberon.Mod, and its sibling SYSTEM.REG in Kernel.Mod, Modules.Mod, System.Mod, as well as in the bootloader. SYSTEM.H, probably another undocumented feature, is used in Kernel.Mod. Hence, without undocumented features, no Oberon system as we know it.
by gray
Wed Jun 14, 2023 1:08 pm
Forum: Astrobe for FPGA RISC5
Topic: SYSTEM.LDREG
Replies: 4
Views: 84635

Re: SYSTEM.LDREG

Just re-reading some old forum posts... and it occurred to me that, undocumented or not, SYSTEM.LDREG is arguably the most central feature of the compiler. Without it, the system would not even boot. See the bootloader, it's literally the first instruction the system executes. :)
by gray
Fri Jun 02, 2023 6:17 am
Forum: Astrobe for FPGA RISC5
Topic: Embedded Project Oberon on Altera FPGA
Replies: 0
Views: 8907

Embedded Project Oberon on Altera FPGA

I have implemented the Embedded Project Oberon (EPO) RISC5 CPU and environment in an Intel Altera FPGA, specifically, using the Terasic Cyclone V GX Starter Kit board [1]. It's a nice board in the same price range as the Digilent Arty A7 100, with lots of LEDs, switches, buttons, SRAM, seven segment...
by gray
Thu Apr 20, 2023 5:16 am
Forum: Astrobe for FPGA RISC5
Topic: Stack Trace
Replies: 0
Views: 13150

Stack Trace

I have always found a "stack trace", ie. the display of the chain of procedure calls that lead to an error, very useful to find the causes of run-time problems. This chain is unrolled by walking the stack backwards from the error point -- or from any state of calls -- frame by frame using the frame ...
by gray
Mon Feb 07, 2022 6:34 am
Forum: Astrobe for FPGA RISC5
Topic: Register R13
Replies: 2
Views: 8542

Re: Register R13

Thanks for the pointers. I don't have intention to change the compiler to use R13, but I am grinding my teeth on an in-circuit debugger, and an otherwise unused register could be handy from assembly code. ;)
by gray
Fri Feb 04, 2022 9:13 am
Forum: Astrobe for FPGA RISC5
Topic: Register R13
Replies: 2
Views: 8542

Register R13

ORG.incR allocates registers up to R11. R12 is MT, R14 is SP, and R15 is LNK. What about R13, may I use it, or does it have a special purpose as well?
by gray
Fri Feb 04, 2022 9:07 am
Forum: Astrobe for FPGA RISC5
Topic: SYSTEM.LDREG
Replies: 4
Views: 84635

SYSTEM.LDREG

The Astrobe RISC5 compiler creates erroneous code in the following case: PROCEDURE P; VAR i: INTEGER; BEGIN i := 0; SYSTEM.LDREG(i, 13) END P; The procedure compiles without error message, but the code created is: 4400000DH MOV r4, r0, 13 Evidently, the target register number must be a constant, as ...