Search found 102 matches
- Mon Dec 18, 2023 10:13 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Buffer Address for DMA
- Replies: 3
- Views: 9739
Buffer Address for DMA
To avoid busy-waiting at a serial output peripheral (USART), I am implementing buffered text output to a terminal. The intention is to use the DMA peripheral on the M0. Among other configuration, the DMA channel expects 1) a memory address of the buffer, and 2) the number of data items to transfer f...
- Fri Nov 17, 2023 9:54 am
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Interrupt Handlers
- Replies: 2
- Views: 8302
Re: Interrupt Handlers
Wow. Smart. I am impressed. Thanks for that.
- Thu Nov 16, 2023 12:26 pm
- Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
- Topic: Interrupt Handlers
- Replies: 2
- Views: 8302
Interrupt Handlers
For the Cortex-M0, the prologue and epilogue generated for interrupt handlers is the same as for normal parameterless procedures. That is, they are the same for PROCEDURE p0; END p0; 0B500H push { lr } 046C0H nop 0BD00H pop { pc } 046C0H nop and PROCEDURE p1[0]; END p1; 0B500H push { lr } 046C0H nop...
- Sat Jun 17, 2023 4:41 am
- Forum: Astrobe for FPGA RISC5
- Topic: SYSTEM.LDREG
- Replies: 4
- Views: 92207
Re: SYSTEM.LDREG
SYSTEM.LDREG is also used in Oberon.Mod, and its sibling SYSTEM.REG in Kernel.Mod, Modules.Mod, System.Mod, as well as in the bootloader. SYSTEM.H, probably another undocumented feature, is used in Kernel.Mod. Hence, without undocumented features, no Oberon system as we know it.
- Wed Jun 14, 2023 1:08 pm
- Forum: Astrobe for FPGA RISC5
- Topic: SYSTEM.LDREG
- Replies: 4
- Views: 92207
Re: SYSTEM.LDREG
Just re-reading some old forum posts... and it occurred to me that, undocumented or not, SYSTEM.LDREG is arguably the most central feature of the compiler. Without it, the system would not even boot. See the bootloader, it's literally the first instruction the system executes. :)
- Fri Jun 02, 2023 6:17 am
- Forum: Astrobe for FPGA RISC5
- Topic: Embedded Project Oberon on Altera FPGA
- Replies: 0
- Views: 19286
Embedded Project Oberon on Altera FPGA
I have implemented the Embedded Project Oberon (EPO) RISC5 CPU and environment in an Intel Altera FPGA, specifically, using the Terasic Cyclone V GX Starter Kit board [1]. It's a nice board in the same price range as the Digilent Arty A7 100, with lots of LEDs, switches, buttons, SRAM, seven segment...
- Thu Apr 20, 2023 5:16 am
- Forum: Astrobe for FPGA RISC5
- Topic: Stack Trace
- Replies: 0
- Views: 23384
Stack Trace
I have always found a "stack trace", ie. the display of the chain of procedure calls that lead to an error, very useful to find the causes of run-time problems. This chain is unrolled by walking the stack backwards from the error point -- or from any state of calls -- frame by frame using the frame ...
- Mon Feb 07, 2022 6:34 am
- Forum: Astrobe for FPGA RISC5
- Topic: Register R13
- Replies: 2
- Views: 13823
Re: Register R13
Thanks for the pointers. I don't have intention to change the compiler to use R13, but I am grinding my teeth on an in-circuit debugger, and an otherwise unused register could be handy from assembly code.
- Fri Feb 04, 2022 9:13 am
- Forum: Astrobe for FPGA RISC5
- Topic: Register R13
- Replies: 2
- Views: 13823
Register R13
ORG.incR allocates registers up to R11. R12 is MT, R14 is SP, and R15 is LNK. What about R13, may I use it, or does it have a special purpose as well?
- Fri Feb 04, 2022 9:07 am
- Forum: Astrobe for FPGA RISC5
- Topic: SYSTEM.LDREG
- Replies: 4
- Views: 92207
SYSTEM.LDREG
The Astrobe RISC5 compiler creates erroneous code in the following case: PROCEDURE P; VAR i: INTEGER; BEGIN i := 0; SYSTEM.LDREG(i, 13) END P; The procedure compiles without error message, but the code created is: 4400000DH MOV r4, r0, 13 Evidently, the target register number must be a constant, as ...